(1) Field of the Invention
The present invention relates to a method used to fabricate a semiconductor device, and more specifically to a method used to connect an overlying bit line structure to an underlying region of a transfer gate transistor.
(2) Description of Prior Art
The objective of increasing semiconductor device performance, while still reducing the manufacturing cost of these same devices, has been successfully addressed via micro-miniaturization, or the ability to fabricate semiconductor devices, with sub-micron features. Micro-miniaturization has been in part realized via advances in specific semiconductor fabrication disciplines such as photolithography and dry etching. The use of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials, have resulted in the routine attainment of sub-micron images in photoresist layers. In addition the development of more advanced dry etching tools, and processes, have allowed the sub-micron images in masking photoresist layers to be successfully transferred to underlying materials, used for the fabrication of semiconductor devices. However structural aspects of advanced semiconductor devices still have to be addressed to take advantage of micro-miniaturization.
One example of a structural component, needed to be addressed to benefit from micro-miniaturization, is the conductive structure, used to connect an overlying bit line structure, of a semiconductor memory device, to an underlying source and drain region of a transfer gate transistor. Several techniques, such as the use of a narrow polysilicon plug, placed between the bit line structure and the underlying source and drain region, have been used. However a placing of the narrow polysilicon plug, on the underlying source and drain region, and then overlaying a bit line structure on the underlying polysilicon plug structure, requires tight layer to layer, photolithographic overlay, sometimes difficult to achieve using sub-micron features. A conventional landing pad, placed on an underlying polysilicon plug structure, although allowing an easier target for placement of an overlying bit line structure, however results in an increase in step height, adversely influencing subsequent patterning procedures.
This invention will describe a process used to form a damascene landing pad, for use as the conductive connection between an overlying bit line structure, for a semiconductor memory device, and the underlying source and drain region of a transfer gate transistor. This invention will describe a first embodiment in which the design of the damascene landing pad contacts an underlying source and drain region, in an active device region of the semiconductor device, but also extends to overlay a non-active region of the semiconductor device, allowing this extended region of the damascene landing pad to be contacted by the overlying bit line structure. A second embodiment of this invention describes an enlarged region of the damascene landing pad, again overlying a non-active device region of the semiconductor device, and now allowing an easier target for the overlying bit line structure to find. Prior art such as Shoda, in U.S. Pat. No. 5,529,953, describes a process for forming both studs and interconnect structures, in an opening in an insulator layer. However that prior art does not describe the desired method of forming a damascene landing pad, with the desired extensions used for contact by an overlying bit line structure.